1. Field of the Invention
The present invention generally relates to automated testing of integrated circuits and, more specifically, to power droop reduction via clock gating for at-speed scan testing.
2. Description of the Related Art
As transistor geometries decrease in size and integrated circuit device surface areas increase, the number of transistors per device increases dramatically. Automatic test pattern generation (ATPG) testing of such a device during the manufacturing process typically employs two phases. The first phase (referred to herein as the “scan-load phase”) is used to initialize the device to a known state for a particular test cycle. During the scan-load phase, relatively few transistors are being switched, and the device enters a quiescent, low-leakage current phase of operation. The second phase (referred to herein as the “capture phase”) sends one or more sets of clock pulses through the device to exercise the device at a rated speed. During the capture phase, a relatively large quantity of the device's transistors are being switched at a rated speed, and the device shifts into an active phase of operation, with a correspondingly high demand for current from the device's power grid.
A rapid shift from the scan-load (quiescent) phase to the capture (active) phase causes a sudden demand for a large amount of current from the power grid of the device. As a result, the power grid may temporarily experience an inductive reaction to the sudden demand for current. The inductive reaction, in turn, causes a power droop on the power grid of the device. Such a power droop may cause the device to fail the at-speed test or to operate at a slower speed during the test. Such a failure or reduction in operational speed, however, may amount to a false negative. In normal operation, an integrated circuit device typically does not experience a rapid shift from quiescent to active states, and does not experience the same power droop as is characteristic during automated testing. In other words, the failure of the device during at-speed testing does not mean the device fails to meet the requirements for normal operation.
One potential solution is to test the device at a lower speed. Testing at a lower speed allows the device allows the device to recover from the large current demand when transitioning from the scan-load phase to the capture phase, prior to clocking the device and capturing the test result. One problem with this approach is testing the device at a lower speed increases test times. Another potential solution is to switch fewer transistors at a time during automated testing. One problem with this approach is that a higher number of test vectors is required to test the device, which, in turn, increases device test times.
As the foregoing illustrates, what is needed in the art is a technique that reduces power droop during at-speed testing of devices, such as integrated circuits.